-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- PROGRAM "Quartus II"
-- VERSION "Version 7.2 Build 203 02/05/2008 Service Pack 2 SJ Full Version"

LIBRARY ieee;
USE ieee.std_logic_1164.all; 
use ieee.std_logic_unsigned.all;

ENTITY nextpc IS 
	port
	(
		jump :  IN  STD_LOGIC;
		branch :  IN  STD_LOGIC;
		INSTR :  IN  STD_LOGIC_VECTOR(31 downto 0);
		PC :  IN  STD_LOGIC_VECTOR(31 downto 0);
		NPC :  OUT  STD_LOGIC_VECTOR(31 downto 0)
	);
END nextpc;

ARCHITECTURE bdf_type OF nextpc IS 
	signal jpc, vpc, branchaddr: std_logic_vector(31 downto 0);
	signal imm: std_logic_vector(15 downto 0);
	signal sign : std_logic;	
	constant four: std_logic_vector(31 downto 0) :=x"00000004";
BEGIN
	vpc <= pc + four;
	sign <= instr(15);
	extention: for i in 0 to 15 generate
		imm(i) <= sign;
	end generate;
	branchaddr <= pc + (imm(13 downto 0)&instr(15 downto 0)&"00");	
	jpc <= pc(31 downto 28)&instr(25 downto 0)&"00" when jump='1' else branchaddr;
	npc <= jpc when (branch='1' or jump='1') else vpc;
END; 